(1) Field of the Invention
This invention relates to a semiconductor memory device and, more particularly, to a twin-cell type semiconductor memory device for storing data in a pair of memory cells as complementary information.
(2) Description of the Related Art
With the improvement of the performance of electronic devices, such as portable devices, highly reliable memories in which low power consumption, large capacity, and a high integration level can be realized have been needed in recent years.
A memory cell in semiconductor memory devices of a dynamic random access memory (DRAM) type has a simple structure. That is to say, it includes one cell transistor and one capacitor. Therefore, with semiconductor memory devices of a DRAM type a high integration level and large capacity can be realized easily. As a result, it is hoped that semiconductor memory devices of a DRAM type will be applied more widely and that their performance will be improved further.
In addition, twin-cell type DRAMs in which data is stored in a pair of memory cells as complementary information corresponding to the high level (H level) and the low level (L level) have been suggested to, for example, reduce power consumed in DRAMs (refer to, for example, Japanese Unexamined Patent Publication No. 2001-143463 (the paragraph numbers [0026]–[0032] and FIG. 1)).
FIGS. 8(A) and 8(B) are simplified views showing the arrangement of memory cells in a conventional semiconductor memory device of a DRAM type. FIG. 8(A) is a simplified view showing the arrangement of memory cells in a single-cell semiconductor memory device of a DRAM type. FIG. 8(B) is a simplified view showing the arrangement of memory cells in a twin-cell semiconductor memory device of a DRAM type.
Both in a single-cell type semiconductor memory device 100 and in a twin-cell type semiconductor memory device 101, memory cells MC each including one cell transistor and one cell capacitor (1T/1C structure) are located at positions where bit lines BL1, /BL1, BL2, and /BL2 and a word line WL intersect alternately. The same cell array is used in the semiconductor memory devices 100 and 101, so cells are arranged in the same way. The semiconductor memory devices 100 and 101 differ in how to connect the bit lines BL1, /BL1, BL2, and /BL2 and sense amplifiers 110 and 111. In the single-cell type semiconductor memory device 100 shown in FIG. 8(A), the bit lines BL1 and /BL1 pair and are connected to the sense amplifier 111. Similarly, the bit lines BL2 and /BL2 pair and are connected to the sense amplifier 110. On the other hand, in the twin-cell type semiconductor memory device 101 shown in FIG. 8(B), the bit lines BL2, BL1, /BL2, and /BL1 are located in that order from the top. The bit lines BL1 and /BL1 pair and are connected to the sense amplifier 110. The bit lines BL2 and /BL2 pair and are connected to the sense amplifier 111.
Information held in each of areas E20, E21, E22, and E23 shown in FIGS. 8(A) and 8(B) will be treated as a piece of data when one word line WL is driven. That is to say, in the area E20 shown in FIG. 8(A), the potential of the bit line BL1 to which a memory cell MC is connected and the potential of the bit line /BL1 (which holds reference potential) to which a memory cell MC is not connected are compared by the sense amplifier 111 and 1-bit data is read. Similarly, in the area E21, the potential of the bit lines BL2 and /BL2 are compared by the sense amplifier 110 and 1-bit data is read. In the area E22 shown in FIG. 8(B), the potential of the complementary bit lines BL2 and /BL2 connected to the gates of a pair of memory cells MC where complementary information has been stored are compared by the sense amplifier 110 and 1-bit data is read. Similarly, in the area E23, the potential of the complementary bit lines BL1 and /BL1 are compared by the sense amplifier 111 and 1-bit data is read.
In the twin-cell type semiconductor memory device 101 shown in FIG. 8(B), only the sense amplifier 110 is activated to read data from the area E22. In this case, there is no need to activate the sense amplifier 111. On the other hand, only the sense amplifier 111 is activated to read data from the area E23. There is no need to activate the sense amplifier 110. Moreover, in the case of reading, complementary information stored in a pair of memory cells MC and corresponding to the H and L levels is read by the complementary bit lines BL1 and /BL1 or the complementary bit lines BL2 and /BL2. This will give a large margin for holding data, compared with the single-cell type semiconductor memory device 100 in which a comparison is made between the potential of a bit line and reference potential. As a result, a refresh cycle can be lengthened and power consumption can be reduced.
There are two kinds of layouts of a cell array in the semiconductor memory devices 100 and 101 shown in FIG. 8: capacitor under bitline (CUB) structure in which cell capacitors are formed under bit lines and capacitor over bitline (COB) structure in which cell capacitors are formed over bit lines.
With the CUB structure, the process for forming cell capacitors comes before the process for forming bit lines. On the other hand, with the COB structure, the process for forming bit lines comes before the process for forming cell capacitors.
FIGS. 9(A) and 9(B) are a view showing a pattern of the layout of a cell array in a conventional semiconductor memory device having the CUB structure and a schematic sectional view of the semiconductor memory device. FIG. 9(A) is a view showing a pattern of the layout of a cell array in a semiconductor memory device having the CUB structure. FIG. 9(B) is a fragmentary cross sectional view taken along the line C–C′ of FIG. 9(A).
The layout pattern shown in FIG. 9(A) can be applied both to the single-cell type semiconductor memory device 100 shown in FIG. 8(A) and to the twin-cell type semiconductor memory device 101 shown in FIG. 8(B), but descriptions of a twin-cell type semiconductor memory device will now be given.
On a layout pattern for a semiconductor memory device 101a having the CUB structure, bit line patterns BLp1, /BLp1, BLp2, and /BLp2 indicated by dotted lines and a plurality of word line patterns WLp are located like a grid and substrate diffusion layer patterns 150p located in the same direction as the bit line patterns BLp1, /BLp1, BLp2, and /BLp2, capacitor patterns 151p, and contact plug patterns 152p and 153p are arranged as areas corresponding to memory cells MC shown in FIG. 8. As shown in FIG. 9(B), the semiconductor memory device 101a fabricated by the use of this layout pattern includes diffusion layers 150a and 150b formed in a substrate 154, capacitors 151 formed under bit lines BL1, /BL1, BL2, and /BL2, contact plugs 152 for connecting a diffusion layer 150b and a capacitor 151, and contact plugs 153 for connecting a diffusion layer 150a and the bit line BL1, /BL1, BL2, or /BL2. Because of restrictions regarding fabrication, each capacitor 151 will be formed at a certain distance (corresponding to the width of one word line, in this example) from a contact plug 153 for connecting a diffusion layer 150a and from the next capacitor 151. Each of areas E25a, E25b, E26a, and E26b in FIG. 9(A) enclosed with a dashed line corresponds to one memory cell MC having the 1T/1C structure. The areas E25a and E25b pair and form a twin cell. Similarly, the areas E26a, and E26b pair and form a twin cell.
It is assumed that the substrate 154 is a p-type one and that the diffusion layers 150a and 150b which will function as a drain or a source are n-type ones. Then, for example, an oxide film (not shown) will be formed beneath word lines WL with these word lines WL as gate electrodes. As a result, n-channel metal oxide semiconductor field effect transistors (MOSFETs) will be formed.
In the above example, stack capacitors have been used to form CUB structure. However, trench capacitors may be used instead. Descriptions of a case where trench capacitors are used will be omitted.
FIGS. 10(A) and 10(B) are a view showing a pattern of the layout of a cell array in a conventional semiconductor memory device having the COB structure and a schematic sectional view of the semiconductor memory device. FIG. 10(A) is a view showing a pattern of the layout of a cell array in a semiconductor memory device having the COB structure. FIG. 10(B) is a fragmentary cross sectional view taken along the line D–D′ of FIG. 10(A).
Now, descriptions of a twin-cell type semiconductor memory device having the COB structure will be given. This is the same with the semiconductor memory device 101a having the CUB structure.
On a layout pattern for a semiconductor memory device 101b having the COB structure, bit line patterns BLp1, /BLp1, BLp2, and /BLp2 indicated by dotted lines and a plurality of word line patterns WLp are located like a grid and substrate diffusion layer patterns 160p located obliquely to the bit line patterns BLp1, /BLp1, BLp2, and /BLp2, capacitor patterns 161p, and contact plug patterns 162p and 163p are arranged as areas corresponding to memory cells MC shown in FIG. 8. As shown in FIG. 10(B), the semiconductor memory device 101b fabricated by the use of this layout pattern includes diffusion layers 160a and 160b formed in a substrate 164, capacitors 161 formed over bit lines BL1, /BL1, BL2, and /BL2, contact plugs 162 for connecting a diffusion layer 160b and a capacitor 161, and contact plugs 163 for connecting a diffusion layer 160a and the bit line BL1, /BL1, BL2, or /BL2. Because of structural restrictions, each capacitor 161 will be formed at a certain distance (corresponding to the width of one word line, in this example) from the next capacitor 161. Areas E27a and E27b in FIG. 10(A) enclosed with a dashed line pair and form a twin cell. Similarly, areas E28a and E28b in FIG. 10(A) enclosed with a dashed line pair and form a twin cell.
It is assumed that the substrate 164 is a p-type one and that the diffusion layers 160a and 160b which will function as a drain or a source are n-type ones. This is the same with the semiconductor memory device 101a having the CUB structure. Then, for example, an oxide film (not shown) will be formed beneath word lines WL with these word lines WL as gate electrodes. As a result, n-channel MOSFETs will be formed.
Moreover, it is assumed that the minimum fabrication dimension in FIGS. 9 and 10 is F (corresponding to the width of a word line WL and a space between adjacent word lines). Then 1T/1C requires an area of 8F2 both in the CUB structure and in the COB structure.
FIGS. 11(A) and 11(B) are circuit diagrams of conventional semiconductor memory devices. FIG. 11(A) is a circuit diagram of a conventional semiconductor memory device having the CUB structure. FIG. 11(B) is a circuit diagram of a conventional semiconductor memory device having the COB structure.
With semiconductor memory devices 101a and 101b, each of memory cells MC shown in FIG. 8 includes a metal oxide semiconductor (MOS) FET (cell transistor) Tr and a cell capacitor C. One input-output terminal (drain or source) of the cell transistor Tr is connected to one of bit lines BL1, /BL1, BL2, and /BL2, the other input-output terminal of the cell transistor Tr is connected to one terminal of the cell capacitor C, and the gate of the cell transistor Tr is connected to a word line WL. The potential of the other terminal of the cell capacitor C is equal to cell plate potential (for example, potential between the L and H levels of power supply potential). Each of areas E29, E30, E31, and E32 enclosed with a dashed line is a twin cell made up of a pair of memory cells MC each having the 1T/1C structure.
When a word line WL is selected and driven, cell transistors Tr the gates of which are connected to the word line WL turn on and the bit line BL1 and /BL1 or the bit lines BL2 and /BL2 and cell capacitors C are electrically connected. As shown in FIG. 8, the bit lines BL1 and /BL1 are connected to the sense amplifier 111 and the bit lines BL2 and /BL2 are connected to the sense amplifier 110. As a result, complementary information is read.
As described above, however, the same cell array that is used in a single-cell type semiconductor memory device is adopted in the conventional twin-cell type semiconductor memory device 101. Therefore, typical cells in single-cell type semiconductor memory devices are 8F2 in area, while typical cells in conventional twin-cell type semiconductor memory devices are 16F2 in area. That is to say, the area of cell arrays in conventional twin-cell type semiconductor memory devices is substantially twice that of cell arrays in single-cell type semiconductor memory devices. This leads to an increase in the total area of chips in semiconductor memory devices.
In addition, if a layout like the one shown in FIG. 10 is adopted and the word line WL adjacent to the diffusion layer 160b is driven, then electric charges in the capacitor 161 will leak out through the diffusion layer 160b. This is a problem specific to volatile memories, such as DRAMs. Data may be destroyed, especially if a memory cell MC which includes the capacitor 161 is in a standby state and the above word line WL for the next memory cell MC is activated frequently.